A cross-sectional view of the structure of an LDMOS transistor disclosed in U.S. Pat. No. 4,682,405 is shown in FIG. 1. The LDMOS transistor has an N type substrate 10, a V-shaped trench 11, a P type body region 12, an N+ source region 13, a gate electrode 14, an N+ drain region 15, gate oxide 16, an oxide layer 17, a source electrode metal contact 18, and a drain electrode metal contact 19. In this structure, the V-shape trench 11 is used to reduce the dimension of the entire LDMOS transistor. However, since the N+ source region 13, the P type body region 12, and the N type substrate 10 form a vertical parasitic NPN transistor, and the vertically projected area of the N+ source region 13 is relatively large, the leakage caused by the parasitic NPN transistor is relatively large and its propensity to cause latch-up problems is a drawback.